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for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. general description the MAX5180 contains two 10-bit, simultaneous- update, current-output digital-to-analog converters (dacs) designed for superior performance in communi- cations systems requiring analog signal reconstruction with low distortion and low-power operation. the max5183 provides equal specifications, with on-chip precision resistors for voltage output operation. the devices are designed for 10pvs glitch operation to min- imize unwanted spurious signal components at the out- put. an on-board 1.2v bandgap circuit provides a well-regulated, low-noise reference that can be dis- abled for external reference operation. the MAX5180/max5183 are designed to provide a high level of signal integrity for the least amount of power dis- sipation. the dacs operate from a single supply of 2.7v to 3.3v. additionally, these dacs have three modes of operation: normal, low-power standby, and complete shutdown, which provides the lowest possible power dis- sipation with 1? (max) shutdown current. a fast wake- up time (0.5?) from standby mode to full dac operation conserves power by activating the dacs only when required. the MAX5180/max5183 are packaged in a 28-pin qsop and are specified for the extended (-40? to +85?) temperature range. for lower-resolution, dual 8-bit versions, refer to the max5186/max5189 data sheet. applications signal reconstruction of i and q transmit signals digital signal processing arbitrary waveform generation (awg) imaging features ? 2.7v to 3.3v single-supply operation ? wide spurious-free dynamic range: 70db at f out = 2.2mhz ? fully differential outputs for each dac ? ?.5% fsr gain mismatch ? ?.2 phase mismatch ? low-current standby or full-shutdown modes ? internal 1.2v low-noise bandgap reference ? small 28-pin qsop package MAX5180/max5183 dual, 10-bit, 40mhz, current/voltage simultaneous-output dacs ________________________________________________________________ maxim integrated products 1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 cref2 out2p out2n refo refr dgnd d3 dv dd d9 d8 d7 d6 d5 d4 d2 d1 d0 ren n.c. clk cs pd dacen av dd agnd out1n out1p cref1 qsop top view MAX5180 max5183 19-1577; rev 4; 12/03 part MAX5180 beei -40? to +85? temp range pin-package 28 qsop pin configuration ordering information max5183 beei -40? to +85? 28 qsop
MAX5180/max5183 dual, 10-bit, 40mhz, current/voltage simultaneous-output dacs 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (av dd = dv dd = 3v ?0%, agnd = dgnd = 0, f clk = 40mhz, i fs = 1ma, 400 ? differential output, c l = 5pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd , dv dd to agnd, dgnd .................................-0.3v to +6v digital inputs to dgnd.............................................-0.3v to +6v out1p, out1n, out2p, out2n, cref1, cref2 to agnd ...................................................-0.3v to +6v v ref to agnd ..........................................................-0.3v to +6v agnd to dgnd.....................................................-0.3v to +0.3v av dd to dv dd .................................................................... ?.3v maximum current into any pin............................................50ma continuous power dissipation (t a = +70?) 28-pin qsop (derate 9.00mw/? above +70?)....... 725mw operating temperature range max518_beei.................................................-40? to +85? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) ................................ +300? -8 +8 max5183 MAX5180 f clk = 40mhz dacen = 0, MAX5180 only f out = 2.2mhz f out = 2.2mhz, t a =+25 c all 0s to all 1s f out = 2.2mhz f clk = 40mhz to ?.5lsb error band guaranteed monotonic (note 1) f clk = 40mhz conditions ? -1 1 output leakage current v -0.3 0.8 voltage compliance of output mv 400 v fs full-scale output voltage degrees ?.15 phase mismatch between dac outputs %fsr ?.5 ? gain mismatch between dac outputs pa/ hz 10 output noise nvs 50 clock and data feedthrough db -60 dac-to-dac output isolation 59 db 61 snr signal-to-noise ratio to nyquist -68 -63 dbc -70 thd total harmonic distortion to nyquist lsb -2 ?.5 +2 inl integral nonlinearity bits 10 n resolution 57 70 dbc 72 sfdr spurious-free dynamic range to nyquist pv-s 10 glitch impulse ns 25 output settling time lsb -1 ?.5 +1 dnl differential nonlinearity lsb -2 +2 zero-scale error lsb -40 ?5 +40 full-scale error units min typ max symbol parameter MAX5180 only MAX5180 only ? 400 r l dac external output resistor load ma 0.5 1 1.5 i fs full-scale output current f out = 550khz f out = 2.2mhz, t a =+25 c f out = 550khz f out = 2.2mhz, t a =+25 c f out = 550khz f out = 2.2mhz, t a =+25 c dynamic performance analog output
MAX5180/max5183 dual, 10-bit, 40mhz, current/voltage simultaneous-output dacs _______________________________________________________________________________________ 3 electrical characteristics (continued) (av dd = dv dd = 3v ?0%, agnd = dgnd = 0, f clk = 40mhz, i fs = 1ma, 400 ? differential output, c l = 5pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) conditions units min typ max symbol parameter pd = 1, dacen = x, digital inputs at 0 or dv dd (x = don? care) pd = 0, dacen = 0, digital inputs at 0 or dv dd pd = 0, dacen = 1, digital inputs at 0 or dv dd pd = 0, dacen = 1, digital inputs at 0 or dv dd ? 0.5 1.0 i shdn shutdown current ma 1.0 1.5 i standby standby current ma 4.2 5.0 i dvdd digital supply current v 2.7 3.3 dv dd digital power-supply voltage ma 2.7 5.0 i avdd analog supply current v 2.7 3.3 av dd analog power-supply voltage ma/ma 8 current gain (i fs / i ref ) mv/v 0.5 reference supply rejection ? 10 i refout reference output drive capability ppm/? 50 tcv ref output voltage temperature drift v 1.12 1.2 1.28 v ref output voltage range v in = 0 or dv dd ns 0 t dh2 dac2 clk fall to data hold time ns 0 t dh1 dac1 clk rise to data hold time ns 10 t ds2 dac2 data to clk fall setup time ns 10 t ds1 dac1 data to clk rise setup time pf 10 c in digital input capacitance ? ? i in digital input current v 0.8 v il digital input voltage low v 2 v ih digital input voltage high ns 10 t cl clock low time ns 10 t ch clock high time ns 25 t cp clock period ? 50 pd fall time to v out_ ? 0.5 dacen rise time to v out_ ns 5 cs fall to clk fall time ns 5 cs fall to clk rise time reference power requirements logic inputs and outputs timing characteristics
1.5 2.0 3.0 2.5 3.5 4.0 -40 -15 10 35 60 85 analog supply current vs. temperature MAX5180/83-04 temperature (?) analog supply current (ma) MAX5180 max5183 0 2 6 4 8 10 2.5 3.5 3.0 4.0 4.5 5.0 5.5 digital supply current vs. supply voltage MAX5180/83-05 supply voltage (v) digital supply current (ma) max5183 MAX5180 0 1 3 2 4 5 -40 -15 10 3 56085 digital supply current vs. temperature MAX5180/83-06 temperature (?) digital supply current (ma) MAX5180 max5183 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 0 128 256 384 512 640 768 896 1024 integral nonlinearity vs. input code MAX5180/83-01 digital input code inl (lsb) 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 0128 256 384 512 640 768 896 1024 differential nonlinearity vs. input code MAX5180/83-02 digital input code dnl (lsb) 2.45 2.47 2.51 2.49 2.53 2.55 2.5 3.5 3.0 4.0 4.5 5.0 5.5 analog supply current vs. supply voltage MAX5180/83-03 supply voltage (v) supply current (ma) MAX5180 max5183 560 570 590 580 600 610 2.5 3.5 3.0 4.0 4.5 5.0 5.5 standby current vs. supply voltage MAX5180/83-07 supply voltage (v) standby current ( a) max5183 MAX5180 540 560 550 580 570 590 600 -40 10 -15 35 60 85 standby current vs. temperature MAX5180/83-08 temperature (?) standby current ( a) MAX5180 max5183 0.45 0.55 0.50 0.60 0.65 0.70 0.75 0.80 2.5 3.5 3.0 4.5 4.0 5.0 5.5 shutdown current vs. supply voltage MAX5180/83-09 supply voltage (v) shuitdown current ( a) MAX5180 max5183 t ypical operating characteristics (av dd = dv dd = 3v, agnd = dgnd = 0, 400 ? differential output, i fs = 1ma, c l = 5pf, t a = +25?, unless otherwise noted.) MAX5180/max5183 dual, 10-bit, 40mhz, current/voltage simultaneous-output dacs 4 _______________________________________________________________________________________
MAX5180/max5183 dual, 10-bit, 40mhz, current/voltage simultaneous-output dacs _______________________________________________________________________________________ 5 1.23 1.24 1.26 1.25 1.27 1.28 2.5 3.5 3.0 4.0 4.5 5.0 5.5 internal reference voltage vs. supply voltage MAX5180/83-10 supply voltage (v) reference voltage (v) max5183 MAX5180 1.23 1.24 1.26 1.25 1.27 1.28 -40 -15 10 35 60 85 internal reference voltage vs. temperature MAX5180/83-11 temperature (?) reference voltage (v) MAX5180 max5183 t ypical operating characteristics (continued) (av dd = dv dd = 3v, agnd = dgnd = 0, 400 ? differential output, i fs = 1ma, c l = 5pf, t a = +25?, unless otherwise noted.) settling time MAX5180/83-15 12.5ns/div out_n 100mv/div out_p 100mv/div 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0246 8101214 16 18 20 output frequency (mhz) output power (dbm) fft plot, dac1 f out = 2.2mhz f clk = 40mhz 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0246 8101214 16 18 20 fft plot, dac2 MAX5180/83-17 output frequency (mhz) output power (dbm) f out = 2.2mhz f clk = 40mhz 40 70 60 50 80 90 100 10 30 25 15 20 35 40 45 50 55 60 MAX5180/83-18 clock frequency (mhz) sfdr (dbc) spurious-free dynamic range vs. clock frequency dac2 dac1 0 1 2 3 4 0200 100 400 300 500 output current vs. reference current MAX5180/83-12 reference current ( a) output current (ma) dynamic response rise time MAX5180/83-13 50ns/div out_p 150mv/div out_n 150mv/div dynamic response fall time MAX5180/83-14 50ns/div out_p 150mv/div out_n 150mv/div
MAX5180/max5183 dual, 10-bit, 40mhz, current/voltage simultaneous-output dacs 6 _______________________________________________________________________________________ 66 70 68 74 72 76 78 500 1100 1300 700 900 1500 1700 1900 2100 2300 MAX5180/83-19 output frequency (khz) sfdr (dbc) spurious-free dynamic range vs. output frequency and clock frequency, dac1 f clk = 60mhz f clk = 40mhz f clk = 30mhz f clk = 10mhz f clk = 50mhz f clk = 20mhz 66 72 70 68 74 76 78 500 1100 1300 700 900 1500 1700 1900 2100 2300 MAX5180/83-20 output frequency (khz) sfdr (dbc) spurious-free dynamic range vs. output frequency and clock frequency, dac2 f clk = 30mhz f clk = 60mhz f clk = 10mhz f clk = 50mhz f clk = 40mhz f clk = 20mhz 62.5 62.0 61.0 60.5 61.5 60.0 0 1500 500 1000 2000 2500 signal-to-noise plus distortion vs. output frequency MAX5180/83-21 ouput frequency (khz) sinad (db) dac2 dac1 -160 -120 -140 -60 -80 -100 -20 0 -40 20 010 5152 02530 MAX5180/83-22 output frequency (mhz) output power (dbm) spurious-free dynamic range vs. output frequency -140 -100 -120 -60 -80 -20 0 -40 20 06 4 210 814 12 18 16 20 MAX5180/83-23 output frequency (mhz) output power (dbm) multitone spurious-free dynamic range vs. output frequency 60 62 64 66 68 70 72 74 0.5 0.75 1 1.25 1.5 spurious-free dynamic range vs. full-scale output current MAX5180/83-24 full-scale output current (ma) sfdr (dbc) t ypical operating characteristics (continued) (av dd = dv dd = 3v, agnd = dgnd = 0, 400 ? differential output, i fs = 1ma, c l = 5pf, t a = +25?, unless otherwise noted.)
MAX5180/max5183 dual, 10-bit, 40mhz, current/voltage simultaneous-output dacs _______________________________________________________________________________________ 7 clock input clk 9 no connect. do not connect to this pin. n.c. 10 active-low reference enable. connect to dgnd to activate on-chip 1.2v reference. ren 11 data bit d0 (lsb) d0 12 data bits d1?8 d1?8 13?0 analog positive supply, 2.7v to 3.3v av dd 5 dac enable, digital input 0: enter dac standby mode with pd = dgnd 1: power-up dac with pd = dgnd x: enter shutdown mode with pd = dv dd (x = don? care) dacen 6 power-down select 0: enter dac standby mode (dacen = dgnd) or power-up dac (dacen = dv dd ) 1: enter shutdown mode. pd 7 active-low chip select cs 8 analog ground agnd 4 negative analog output, dac1. current output for MAX5180; voltage output for max5183. out1n 3 pin positive analog output, dac1. current output for MAX5180; voltage output for max5183. out1p 2 reference bias bypass, dac1 cref1 1 function name reference output refo 25 negative analog output, dac2. current output for MAX5180; voltage output for max5183. out2n 26 positive analog output, dac2. current output for MAX5180; voltage output for max5183. out2p 27 reference bias bypass, dac2 cref2 28 reference input refr 24 digital ground dgnd 23 digital supply, 2.7v to 3.3v dv dd 22 data bit d9 (msb) d9 21 ______________________________________________________________pin description
MAX5180/max5183 dual, 10-bit, 40mhz, current/voltage simultaneous-output dacs 8 _______________________________________________________________________________________ detailed description the MAX5180/max5183 are dual, 10-bit digital-to-ana- log converters (dacs) capable of operating with clock speeds up to 40mhz. each of these dual converters consists of separate input and dac registers, followed by a current source array capable of generating up to 1.5ma full-scale output current (figure 1). an integrat- ed 1.2v voltage reference and control amplifier deter- mine the data converters?full-scale output currents/ voltages. careful reference design ensures close gain matching and excellent drift characteristics. the max5183? voltage output operation features matched 400 ? on-chip resistors that convert the current array current into a voltage. internal reference and control amplifier the MAX5180/max5183 provide an integrated 50ppm/?, 1.2v, low-noise bandgap reference that can be disabled and overridden by an external reference voltage. refo serves either as an external reference input or an integrated reference output. if ren is con- nected to agnd, the internal reference is selected and refo provides a 1.2v output. due to its limited 10? output drive capability, refo must be buffered with an external amplifier, if heavier loading is required. the MAX5180/max5183 also employ a control amplifier designed to simultaneously regulate the full-scale out- put current (i fs ) for both outputs of the devices. the output current is calculated as follows: i fs = 8 i ref where i ref is the reference output current (i ref = v refo/ r set ) and i fs is the full-scale output current. r set is the reference resistor that determines the amplifier? output current on the MAX5180 (figure 2). this current is mirrored into the current-source array where it is equally distributed between matched current segments and summed to valid output current readings for the dacs. the max5183 converts each output current (dac1 and dac2) into an output voltage (v out1 , v out2 ) with two internal, ground-referenced 400 ? load resistors. using the internal 1.2v reference voltage, the max5183? inte- grated reference output current resistor (r set = 9.6k ? ) sets i ref to 125? and i fs to 1ma. 9.6k refr refo 1.2v ref ren current- source array dac 1 switches dac 2 switches 400 ? msb decode clk output latches output latches msb decode *internal 400 ? and 9.6k ? resistors for max5183 only. av dd agnd dacen pd * * * * dv dd dgnd d9?0 cs cref2 MAX5180 max5183 cref1 out2p out1p out2n out1n 400 ? 400 ? 400 ? input latches input latches * figure 1. functional diagram
MAX5180/max5183 dual, 10-bit, 40mhz, current/voltage simultaneous-output dacs _______________________________________________________________________________________ 9 9.6k i fs 0.1 f 10 f av dd r set i ref refr av dd * refo 1.2v bandgap reference current- source array external 1.2v reference *9.6k ? reference current-set resistor internal to max5183 only. use external r set for MAX5180. ren MAX5180 max5183 max6520 agnd agnd agnd r set figure 3. MAX5180/max5183 with external reference r set 9.6k i fs c comp * refr i ref ** refo max4040 +1.2v bandgap reference current- source array *compensation capacitor (c comp 100nf). **9.6k ? reference current-set resistor internal to max5183 only. use external r set for MAX5180. optional external buffer for heavier loads ren MAX5180 max5183 i ref = v ref r set r set agnd agnd agnd figure 2. setting i fs with the internal 1.2v reference and the control amplifier
MAX5180/max5183 dual, 10-bit, 40mhz, current/voltage simultaneous-output dacs 10 ______________________________________________________________________________________ pd (power-down select) dacen (dac enable) power-down mode output state 0 0 standby MAX5180 high-z max5183 agnd 0 1 wake-up last state prior to standby mode 1 x shutdown MAX5180 high-z max5183 agnd table 1. power-down mode selection x = don? care external reference to disable the MAX5180/max5183? internal reference, connect ren to av dd . a temperature-stable, external reference may now be applied to drive the refo pin to set the full-scale output (figure 3). choose a reference capable of supplying at least 150? to drive the bias circuit that generates the cascode current for the cur- rent array. for improved accuracy and drift perfor- mance, choose a fixed output voltage reference such as the 1.2v, 25ppm/? max6520 bandgap reference. standby mode to enter the lower power standby mode, connect digital inputs pd and dacen to dgnd. in standby, both the reference and the control amplifier are active with the current array inactive. to exit this condition, dacen must be pulled high with pd held at dgnd. both the MAX5180 and max5183 typically require 50? to wake up and allow both the outputs and the reference to settle. shutdown mode for lowest power consumption, the MAX5180/max5183 provide a power-down mode in which the reference, control amplifier, and current array are inactive and the dac supply current is reduced to 1?. to enter this mode, connect pd to dv dd . to return to active mode, connect pd to dgnd and dacen to dv dd . table 1 lists the power-down mode selection. about 50? are required for the parts to leave shutdown mode and set- tle to their outputs?values prior to shutdown. timing information the MAX5180/max5183 dual dacs write to their out- puts simultaneously ( figure 4 ). on the falling edge of t ds1 t ds2 t ch t cl t clk t dh1 t dh1 dac 1 (n-1) input sample n-1 for dac 1 input sample n for dac 2 updates dac 1 and dac 2 to n-1 updates dac 1 and dac 2 to n updates dac 1 and dac 2 to n+1 updates dac 1 and dac 2 to n+2 preloads sample n for dac 2 preloads sample n+1 for dac 2 preloads sample n+2 for dac 2 input sample n for dac 1 input sample n+1 for dac 2 input sample n+1 for dac 1 input sample n+2 for dac 2 input sample n+2 for dac 1 input sample n+3 for dac 2 n-2 dac 1 clk dac 2 d0?9 n-1 n-1 n n n+1 n+1 n+2 n+2 n-2 dac 2 (n) dac 1 (n) dac 2 (n+1) dac 1 (n+1) dac 2 (n+2) dac 1 (n+2) dac 2 (n+3) figure 4. timing diagram
MAX5180/max5183 dual, 10-bit, 40mhz, current/voltage simultaneous-output dacs ______________________________________________________________________________________ 11 the clock, the input data for dac2 is preloaded into a latch. on the rising edge of the clock, input data for dac1 is loaded to the dac1 register, and the pre- loaded dac2 data in the latch is loaded to the dac2 register. outputs the MAX5180 outputs are designed to supply full-scale output currents of 1ma into 400 ? loads in parallel with a capacitive load of 5pf. the max5183 features inte- grated 400 ? resistors that restore the array currents to proportional, differential voltages of 400mv. these dif- ferential output voltages can then be used to drive a balun transformer or a low-distortion, high-speed oper- ational amplifier to convert the differential voltage into a single-ended voltage. applications information static and dynamic performance definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on an actual transfer function from either a best straight-line fit (closest approximation to the actual transfer curve) or a line drawn between the end points of the transfer func- tion, once offset and gain errors have been nullified. the MAX5180/max5183 use a straight-line end-point fit for inl (and dnl) and the deviations are measured at every individual step. differential nonlinearity (dnl) differential nonlinearity is the difference between an actual step height and the ideal value of 1 lsb. a dnl error specification no more negative than -1 lsb guar- antees a monotonic transfer function. offset error the offset error is the difference between the ideal and the actual offset current/voltage. for the MAX5180/ max5183, the offset error is the midpoint value of the transfer function determined by the end points of a straight-line end-point fit. this error affects all codes by the same amount. gain error gain error is the difference between the ideal and the actual output value range. this range represents the output when all digital inputs are set to 1 minus the out- put when all digital inputs are set to zero. glitch impulse a glitch is generated when a dac switches between two codes. the largest glitch is usually generated around the midscale transition when the input pattern transitions from 011?11 to 100?00. this occurs due to timing variations between the bits. the glitch impulse is found by integrating the voltage of the glitch at the midscale transition over time. the glitch impulse is usu- ally specified in pv-s. settling time the settling time is the amount of time required from the start of a transition until the dac output settles its new output value to within the converter? specified accuracy. digital feedthrough digital feedthrough is the noise generated on a dac? output when any digital input transitions. proper board layout and grounding will significantly reduce this noise, but there will always be some feedthrough caused by the dac itself. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of the input signal? first four harmonics to the fun- damental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 5 are the amplitudes of the 2nd- through 5th-order harmonics. spurious-free dynamic range (sfdr) sfdr is the ratio of rms amplitude of the carrier fre- quency (maximum signal component) to the rms value of the next-largest noise or harmonic distortion compo- nent. sfdr is usually measured in dbc with respect to the carrier frequency amplitude or in dbfs with respect to the dac? full-scale range. depending on its test condition, sfdr is observed within a predefined win- dow or to nyquist. in the case of the MAX5180/max5183, the sfdr performance is measured for a 0dbfs output amplitude and analyzed within the nyquist window. differential to single-ended conversion the max4108 low-distortion, high-input bandwidth amplifier may be used to generate a voltage from the array current output of the MAX5180. the differential voltage across out1p (or out2p) and out1n (or out2n) is converted into a single-ended voltage by designing an appropriate operational amplifier configu- ration ( figure 5 ). thd vvvv v = +++ ? ? ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 1 log
MAX5180/max5183 dual, 10-bit, 40mhz, current/voltage simultaneous-output dacs 12 ______________________________________________________________________________________ i/q reconstruction in a qam application the MAX5180/max5183? low-distortion supports ana- log reconstruction of in-phase (i) and quadrature (q) carrier components typically used in qam (quadrature amplitude modulation) architectures where i and q data are interleaved on a common data bus. a qam signal is a carrier frequency that is both amplitude and phase modulated, and is created by summing two independently modulated carriers of identical frequency but different phase (90 phase difference). in a typical qam application ( figure 6 ), the modulation occurs in the digital domain and the MAX5180/ max5183? dual dacs may be used to reconstruct the analog i and q components. the i/q reconstruction system is completed by a quad- rature modulator that combines the reconstructed i and q components with in-phase and quadrature phase carrier frequencies, then sums both outputs to provide the qam signal. grounding and power-supply decoupling grounding and power-supply decoupling strongly influ- ence the MAX5180/max5183? performance. unwanted digital crosstalk may couple through the input, refer- ence, power-supply, and ground connections, which may affect dynamic specifications like signal-to-noise ratio or spurious-free dynamic range. in addition, elec- tromagnetic interference (emi) can either couple into or be generated by the MAX5180/max5183. therefore, agnd dgnd out1p cref2 cref1 out1n out2p out2n 0.1 f 0.1 f 0.1 f av dd av dd av dd r set ** *400 ? resistors internal to max5183 only. **MAX5180 only MAX5180 max5183 10 f 3v 3v 0.1 f 0.1 f clk refr refo d0?9 10 f 400 ? * 400 ? * 5v 5v -5v 402 ? 402 ? 402 ? dv dd 402 ? output1 ren 400 ? * 400 ? * -5v 402 ? 402 ? 402 ? 402 ? output2 max4108 max4108 figure 5. differential to single-ended conversion using a low-distortion amplifier
MAX5180/max5183 dual, 10-bit, 40mhz, current/voltage simultaneous-output dacs ______________________________________________________________________________________ 13 grounding and power-supply decoupling guidelines for high-speed, high-frequency applications should be closely followed. first, a multilayer pc board with separate ground and power-supply planes is recommended. high-speed signals should be run on controlled impedance lines directly above the ground plane. since the MAX5180/ max5183 have separate analog and digital ground buses (agnd and dgnd, respectively), the pc board should also have separate analog and digital ground sections with only one point connecting the two. digital signals should run above the digital ground plane, and analog signals should run above the analog ground plane. both devices have two power-supply inputs: analog v dd (av dd ) and digital v dd (dv dd ). each av dd input should be decoupled with parallel 10? and 0.1? ceramic-chip capacitors. these capacitors should be as close to the pin as possible, and their opposite ends should be as close to the ground plane as possible. the dv dd pins should also have separate 10? and 0.1f capacitors adjacent to their respective pins. try to mini- mize analog load capacitance for proper operation. for best performance, it is recommended to bypass cref1 and cref2 with low-esr 0.1? capacitors to av dd . the power-supply voltages should also be decoupled with large tantalum or electrolytic capacitors at the point they enter the pc board. ferrite beads with addi- tional decoupling capacitors forming a pi network can also improve performance. chip information transistor count: 9464 substrate connected to agnd bp filter carrier frequency max2452 if q component bp filter 3v quadrature modulator i component 0 90 3v MAX5180 max5183 dac2 dac1 3v digital signal processor figure 6. using the MAX5180/max5183 for i/q signal reconstruction
MAX5180/max5183 dual, 10-bit, 40mhz, current/voltage simultaneous-output dacs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information qsop.eps

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